This application claims the priority of Korean Patent Application No. 2002-75692, filed Nov. 30, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a 4-bit prefetch-type fast cycle random access memory (FCRAM) having an improved circuit for controlling the writing of data and a method of masking data.
2. Description of the Related Art
In general, a semiconductor memory device includes a memory cell array having a matrix structure. When a row address and a column address are input into such a semiconductor memory device, data are read from or written to a memory cell indicated by the row and column addresses in response to a read control command or a write command.
As the operating speed of systems continues to increase, the operating speed of semiconductor memory devices becomes more likely to limit the performance of systems. In order to address such a limitation, high-performance DRAMs having enhanced operating speed, such as a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, and a fast cycle RAM (FCRAM), have been developed. An example of a conventional FCRAM has been disclosed in U.S. Pat. No. 6,522,600.
In an SDRAM, data can be input and output at one of a rising edge or a falling edge of a clock signal. On the other hand, in a DDR SDRAM, data can be input and output at both a rising edge and a falling edge of a clock signal. Accordingly, the data transmission speed of a DDR SDRAM is two times as fast as the data transmission speed of an SDRAM. In addition, since a DDR SDRAM includes data input/output masking (DQM) pins, the inputting and outputting of data can be disabled according to predetermined latency when a data masking signal is activated.
An example of such a DDR SDRAM is shown in FIG. 1.
FIG. 1 is a block diagram of a DDR SDRAM having a typical data write control function. Specifically, in FIG. 1, an X16 DDR SDRAM, which includes 16 data input/output pins and is thus capable of processing 16 bits of data at the same time, is shown.
Referring to FIG. 1, a DDR SDRAM 100 includes a command decoder 101, an address buffer 102, a control signal generator 103, a memory cell array 104, a row decoder 105, a column decoder 106, a sense amplifier 107, and an input/output control circuit 108.
In addition, the DDR SDRAM 100 further includes data input buffers 109 and 110, data output buffers 111 and 112, a data masking (DM) buffer controller 113, first and second DM buffers 114 and 115, and first and second write controllers 116 and 117.
The command decoder 101 outputs a plurality of control commands including a write command WRITE in response to control signals /CS, /RAS, /CAS, and /WE input from an external source, for example, through control pins 121.
The address buffer 102 transmits a row address and a column address, which are input from an external source through address pins 122, to the row decoder 105 and the column decoder 106, respectively.
The control signal generator 103 activates a control signal CTL in response to the write command WRITE. Core circuits of a DRAM, for example, the row decoder 105, the column decoder 106, the input/output control circuit 108, the data input buffers 109 and 110, and the data output buffers 111 and 112 are controlled by the control signal CTL.
The row decoder 105 decodes the row address and activates a wordline in the memory cell array 104 corresponding to the row address. The column decoder 106 decodes the column address and enables a column select line in the memory cell array 104 corresponding to the column address.
The sense amplifier 107 senses, amplifies, and outputs data read from a selected memory cell.
The input/output control circuit 108 transmits the data amplified by the sense amplifier 107 to the data output buffers 111 and 112 and transmits data input into the data input buffers 109 and 110 to the memory cell array 104.
Data to be written are input into the data input buffers 109 and 110 via data input/output pins 123 and 124, and the data output buffers 111 and 112 output the read data via the data input/output pins 123 and 124.
The DM buffer controller 113 outputs a DM buffer control signal CTL_DMB in response to the write command WRITE. The first and second DM buffers 114 and 115 are turned on in response to the DM buffer control signal CTL_DMB and enable write control signals LDMC and UDMC, respectively, in response to write prevention signals LDM and UDM, respectively, input from an external source via data masking pins 125 and 126.
Here, the write prevention signal LDM is a signal for controlling the inputting of data DQ0 through DQ7 into the data input buffer 109. In addition, the write prevention signal UDM is a signal for controlling the inputting of data DQ8 through DQ15 into the data input buffer 110.
The first and second write controllers 116 and 117 enable buffer control signals WDML and WDMU, respectively, in response to the write control signals LDMC and UDMC, respectively. When the buffer control signal WDML is disabled, the data input buffer 109 is in a high impedance state, during which the data DQ0 through DQ7 are not input into the data input buffer 109. Likewise, when the buffer control signal WDMU is disabled, the data input buffer 110 is in a high impedance state, during which the data DQ8 through DQ15 are not input into the data input buffer 110. Accordingly, it is possible to mask data desired not to be written using the data masking pins 125 and 126.
FIG. 2 is a timing diagram of input and output signals of the DDR SDRAM shown in FIG. 1. As shown in FIG. 2, when the command decoder 101 outputs the write command WRITE in synchronization with a clock signal CLK, the control signal generator 103 enables the control signal CTL in response to the write command WRITE.
In addition, the DM buffer controller 113 enables the DM buffer control signal CTL_DMB in response to the write command WRITE.
The first and second DM buffers 114 and 115 are turned on in response to the DM buffer control signal CTL_DMB and enable the write control signals LDMC and UDMC, respectively, in response to the write prevention signals LDM and UDM, respectively.
In FIG. 2, the write prevention signal LDM is enabled and input when a first write command WRITE is output, and the write prevention signal UDM is enabled and input when a second write command WRITE is output.
As shown in FIG. 2, when the first write command WRITE is output and then the write prevention signal LDM is enabled and input, the write control signal LDMC is enabled. At this moment, the write prevention signal UDM is disabled, and thus the write control signal UDMC is disabled too.
When the write control signal LDMC is enabled, the first write controller 116 enables the buffer control signal WDML in response to the write control signal LDMC.
Since the control signal CTL and the buffer control signal WDML are enabled, the data DQ0 through DQ7 are input into the data input buffer 109.
As shown in FIG. 2, however, the buffer control signal WDMU is disabled, and thus the data DQ8 through DQ15 are not input into the data input buffer 110.
When the second write command WRITE is input, the write prevention signal UDM is enabled and input, and thus the data DQ8 through DQ15 are input into the data input buffer 110. Accordingly, the DDR SDRAM 100 has the function of masking data desired not to be written.
In the meantime, an FCRAM, unlike a DDR SDRAM, does not include data input/output masking pins for masking unwanted data. Accordingly, an FCRAM is also required to have a data masking function.